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SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
2.5.3
RESET, Interrupts, and JTAG Terminal Functions
Table 2-7. RESET, Interrupts, and JTAG Terminal Functions
SIGNAL
NAME
NO.
TYPE (1)
(2)
OTHER (3)
(4)
DESCRIPTION
RESET
External Flag Output. XF is used for signaling other processors in
multiprocessor configurations or XF can be used as a fast general-
purpose output pin.
XF is set high by the BSET XF instruction and XF is set low by the
BCLR XF instruction or by writing to bit 13 of the ST1_55 register. For
–
more information on the ST1_55 register, see the TMS320C55x 3.0
XF
M8
O/Z
DV DDIO
CPU Reference Guide (literature number: SWPU073 ).
BH
IPU
For XF pin behavior at reset, see Section 5.7.2 , Pin Behaviors at Reset .
Note: This pin may consume static power if configured as Hi-Z and not
externally pulled low or high. Prevent current drain by externally
terminating the pin. XF pin is ONLY in the Hi-Z state when doing
boundary scan. Therefore, external termination is probably not required
for most applications.
Device reset. RESET causes the DSP to terminate execution and loads
the program counter with the contents of the reset vector. When
RESET is brought to a high level, the reset vector in ROM at FFFF00h
forces the program execution to branch to the location of the on-chip
RESET
D6
I
DV DDIO
ROM bootloader.
BH
RESET affects the various registers and status bits.
The IPU resistor on this pin can be enabled or disabled via the
PDINHIBR2 register but will be forced ON when RESET is asserted.
JTAG
[For more detailed information on emulation header design guidelines, see the XDS560 Emulator Technical Reference (literature number:
SPRU589 ).]
IEEE standard 1149.1 test mode select. This serial control input is
clocked into the TAP controller on the rising edge of TCK.
If the emulation header is located greater than 6 inches from the
device, TMS must be buffered. In this case, the input buffer for TMS
IPU
needs a pullup resistor connected to DV DDIO to hold the signal at a
TMS
L8
I
DV DDIO
known value when the emulator is not connected. A resistor value of
BH
4.7 k ? or greater is suggested. For board design guidelines related to
the emulation header, see the XDS560 Emulator Technical Reference
(literature number: SPRU589 ).
The IPU resistor on this pin can be enabled or disabled via the
PDINHIBR2 register.
(1)
(2)
(3)
(4)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-
supply current. Prevent this current by externally terminating it or enabling IPD/IPU, if applicable.
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1 , Pullup/Pulldown Resistors .
Specifies the operating I/O supply voltage for each signal
18
Device Overview
Product Folder Links: TMS320C5515
Copyright ? 2010–2013, Texas Instruments Incorporated
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